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NXP Semiconductors /LPC18xx /GPDMA /INTERRSTAT

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Interpret as INTERRSTAT

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (INTERRSTAT0)INTERRSTAT0 0 (INTERRSTAT1)INTERRSTAT1 0 (INTERRSTAT2)INTERRSTAT2 0 (INTERRSTAT3)INTERRSTAT3 0 (INTERRSTAT4)INTERRSTAT4 0 (INTERRSTAT5)INTERRSTAT5 0 (INTERRSTAT6)INTERRSTAT6 0 (INTERRSTAT7)INTERRSTAT7 0RESERVED

Description

DMA Interrupt Error Status Register

Fields

INTERRSTAT0

Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request.
INTERRSTAT1

Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request.
INTERRSTAT2

Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request.
INTERRSTAT3

Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request.
INTERRSTAT4

Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request.
INTERRSTAT5

Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request.
INTERRSTAT6

Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request.
INTERRSTAT7

Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request.
RESERVED

Reserved. Read undefined.

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data